The present invention relates to a method of manufacturing a semiconductor memory device. More specifically, the present invention relates to a process of cleaning a semiconductor memory device.
A semiconductor memory device includes a plurality of gate lines, such as word lines.
The word lines may be disposed parallel to one another on a semiconductor substrate and connected to a plurality of memory cells. Accordingly, as a distance between adjacent word lines decreases, a distance between the memory cells may also decrease. Meanwhile, as the integration density of semiconductor memory devices gradually increases, a distance between word lines is gradually narrowing, and thus interference between memory cells is gradually increasing.
Accordingly, research into techniques for reducing the interference between the memory cells, for example, a technique of forming air gaps between word lines, is progressing at a rapid pace.
To form the air gaps between the word lines, upper portions of the word lines should be covered with an insulating layer, and a cleaning process for removing residue generated during a manufacturing process should be performed after the cleaning process. While the cleaning process may be performed using a dry method, a dry cleaning process makes it difficult to completely remove the residue. Therefore, the cleaning process is typically performed using a wet method. Meanwhile, there may be cases where air gaps are exposed through the insulating layer due to a manufacturing process. In a wet cleaning process, a cleaning solution may flow into the exposed air gaps, thereby causing defects in the semiconductor memory device.
The above-described problems will now be described in detail with reference to the appended drawings.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor memory device.
Referring to FIG. 1, a semiconductor memory device, including a plurality of gate lines 12 formed on a semiconductor substrate 11, air gaps 14 formed between the gate lines 12, and an insulating layer 13 formed on the entire structure may be provided. For example, the plurality of gate lines 12 may functions as word lines. Each of the gate lines 12 may include a stack structure of a tunnel insulating layer, a floating gate, a dielectric layer, and a control gate. The insulating layer 13 may be formed on the entire structure to form the air gaps 14 between the gate lines 12. Thereafter, although not shown in the cross-sectional view of FIG. 1, a contact hole may be formed in a cell region or a peripheral circuit region. The contact hole may be formed by forming a photoresist pattern (not shown) on the insulating layer 13 and performing an etching process using the photoresist pattern as an etch mask. The photoresist pattern may then be removed.
When a strip process for removing the photoresist pattern is performed, residue (or by-products) generated during the etching of the insulating layer 13 may mostly be removed. However, since some residue may still remain, a cleaning process may be performed. Typically, the cleaning process may be performed by a wet method, using a buffered oxide etchant (BOE) solution, which may include hydrofluoric acid (HF) and a buffering agent, such as ammonium fluoride (NH4F).
The BOE solution may have a low viscosity at a high temperature and may have a high viscosity at a low temperature. For example, assuming that deionized water (DIW) has a viscosity of 1 cP, the BOE solution may have a viscosity of about 4.8 cP at a temperature of about 90° C., and a viscosity of about 18 cP at about 25° C. (hereinafter referred to as room temperature).
In addition, if the BOE solution contains a surfactant, and an open region OP is formed in a portion of the insulating layer 13, the BOE solution may permeate more deeply into the air gaps 15 due to the surfactant. Accordingly, even if the BOE solution is dried, the BOE solution may remain within the air gaps 15. A high concentration of sulfuric acid (H2SO4) may be generated due to the remaining BOE solution and fumes (e.g., SO4) may form within the air gaps 15. Furthermore, a portion of the insulating layer 13 formed on sidewalls of the gate lines 12 may be removed due to the BOE solution, thereby allowing the BOE solution to permeate into the semiconductor substrate 11 and the gate lines 12. In particular, since the BOE solution has an acidity of about 6 to 7 pH, the gate lines 12 may be partially oxidized due to hydroxide (OH−) ions or bifluoride (HF2−) ions from the BOE solution, so that the gate lines 12 may be damaged.
FIG. 2 is a photograph of a cross-section of a conventional semiconductor memory device, illustrating conventional problems.
Referring to FIG. 2, as described above with reference to FIG. 1, when gate lines are damaged by a cleaning solution, some of the gate lines may collapse (refer to 21) or have reduced areas (refer to 22), thereby reducing yield and degrading the reliability of semiconductor memory devices.